1. Technical Field
The present disclosure is directed to a method and apparatus that enable an optimum bond pad design for charging-free reference transistor test structures while also taking into account both measurement accuracy and minimum layout space usage.
2. Description of Related Art
Transistor test structures are indispensable in monitoring health of transistors during integrated-circuit (IC) process technology development. However, the size of bond pads required in these test transistors for the measurement purpose is usually quite large, easily introducing strong process charging effect to degrade transistor characteristics during the back-end (BE) IC manufacturing process. This could differentiate characteristics of the transistor test structures from those of the transistors in circuits. The above is particularly true for thick gate-oxide test transistors operating at medium to high chip operation supply voltages in the I/O portion of the circuits. These transistors have gate oxide thickness typically ranging from 40 to 150 Å in order to sustain the higher voltages during the chip operation. They, however, are more vulnerable to the charging damage during the plasma-involved backend IC manufacturing process compared to thin gate-oxide transistors operating at low chip operation supply voltages.
Among transistor-based test structures, reference transistor test structures, due to their significant importance worth further discussion. The reference transistor test structures are essential in monitoring transistor health issues because they serve as a clean benchmark for test structures designed in accordance with specifications (i.e., transistors with various process or device designs). With the reference transistor test structures, performance evaluation for the test structures designed pursuant to the specifications could be accomplished.
The reference transistor test structures must be maintained clean and uncontaminated from the time of their formation in front-end (FE) process until they are tested after end-of-line (EOL). As such, clean transistor basic characteristics such as the parameters of threshold voltage, drive current, off-state leakage, etc. during electrical test (E-test) could be provided.
In order to fend off the charging effect, the reference transistor test structures are traditionally protected at their gates with protection diodes (i.e., junction diodes or gated diodes) at the bond-pad metal layer to prevent charging damage caused by the large-size gate bond pads, and to protect gate oxides. Nonetheless, it has been observed that such arrangement may not always work, and in some case even backfire.
Therefore, the bond pad design for the “charging-free” reference transistor test structures is important and should deserve attention. This present disclosure is the first step in an effort toward the goal of achieving a better bond pad design for the transistor test structures designed for various transistor-health monitoring applications.